Embodiments of the present invention relate to computer technology, and more particularly, to processor architecture.
For many microprocessors, executing a move instruction usually involves moving a value from one register to another register, or moving an immediate to a register. Because of the frequency of such move instructions, processor performance may be increased if move instructions are efficiently processed.
Most instructions operate on several source operands and generate results. They name, either explicitly or through an indirection, the source and destination locations where values are read from or written to. A name may be either a logical (architectural) register or a location in memory.
Usually, the number of physical registers available in a microprocessor exceeds the number of logical registers, so that register renaming may be utilized to increase performance. In particular, for out-of-order processors, register renaming allows instructions to be executed out of their original program order. Thus, for many out-of-order processors, a move instruction is renamed so that logical registers named in the original move instruction are renamed to physical registers.
Renaming a logical register involves mapping a logical register to a physical register. These mappings are stored in a RAT (Register Alias Table). A RAT maintains the latest mapping for each logical register. A RAT is indexed by logical registers, and provides mappings to corresponding physical registers (dependency-tracking).
Illustrated in FIG. 1 is a register renaming and dependency tracking scheme involving three structures: RAT 110, active list (AL) 102, and free list (FL) 104. For each logical register specified by a renamed instruction (or renamed micro-instruction), an unused physical register from FL 104 is allocated and RAT 110 is updated with this new mapping. Physical registers are free to be used again (i.e., reclaimed) once they cannot be referenced anymore by instructions in the current instruction window.
Based upon the data structures depicted in FIG. 1, one method for register reclaiming is to reclaim a physical register only when the instruction that evicted it from RAT 110, i.e., the instruction that created a new mapping to the physical register, retires. As a result, whenever a new mapping updates RAT 110, the evicted old mapping is pushed into AL 102. (An AL entry is associated with each instruction in the instruction window.) When an instruction retires, the physical register of the old mapping recorded in AL 102, if any, is reclaimed and pushed into FL 104. This cycle is depicted in FIG. 1.
For many instructions belonging to the Intel(copyright) Architecture 32-bit (IA-32) instruction set (Intel(copyright) is a registered trademark of Intel Corporation, Santa Clara, Calif.), one of the source registers is also used as the destination register. If the value stored in this source register is needed by subsequent (in program order) instructions, a register-move instruction may be inserted prior to the subsequent instruction to copy the source operand in the source register to another logical location so that it can be accessed by the subsequent instruction. (IA-32 move instructions operating on memory operands are considered load or store instructions.)
Another reason for the insertion of register-move instructions in IA-32 code is to set the parameter values in the appropriate registers prior to a procedure call. The IA-32 Application Binary Interface (ABI) requires parameters for a procedure call to be passed on the stack. However, compilers often use alternate, non-standard, register-based parameter passing, when possible. For RISC instruction set architecture machines, register-move instructions are mainly used for parameter passing.
As a result, the number of register-move instructions may be quite significant in typical IA-32 programs, as well as for programs written for other processor architectures. Therefore, it is useful to provide for the efficient execution of register-move instructions with efficient register renaming and reclaiming schemes.
Embodiments of the present invention are directed to microprocessors that map more than one logical register to the same physical register. For one embodiment, a microprocessor comprises physical registers, a decoder to decode a register-to-register move instruction indicating a source logical register and a destination logical register, and a register allocation table in which the destination logical register is mapped to the same physical register that the source logical register is mapped to. For another embodiment, a counter is associated with each physical register to indicate when a physical register is free. For another embodiments, an immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register already storing the immediate.